FIG. 1 is a circuit diagram showing a conventional switching regulator of a synchronous rectification type. (See, for example, Japanese Laid-Open Patent Application No. 2004-56982.)
The switching regulator of FIG. 1 is a step-down synchronous rectification type, in which a current flows backward from an output terminal 104 to ground GND through an NMOS transistor QN1 at a light load time. In order to prevent such current backflow or reverse current from being generated, the switching regulator of FIG. 1 uses a detector circuit 131 to quickly detect a time for the voltage at the connection K of a PMOS transistor QP1 and the NMOS transistor QN1 to increase across the ground voltage GND again after undershooting the ground voltage GND, and immediately turns OFF the NMOS transistor QN1. As a result, generation of reverse current is prevented, so that power consumption is reduced.
However, according to the switching regulator of FIG. 1, when a reverse current is detected in the detector circuit 131, the NMOS transistor QN1 is turned OFF via an output driver 132. Therefore, there is a delay in time between the detection of the reverse current and the turn-off of the NMOS transistor QN1. This causes the reverse current to flow from the output terminal 104 through a coil L for a longer period of time, thus causing the problem of reduced efficiency.